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The MOSFET in the following circuit is in which configuration? Common Source (CS) Common Drain (CD) Common Gate (CG) None of the mentioned

The MOSFET in the following circuit is in which configuration? Common Source (CS) Common Drain (CD) Common Gate (CG) None of the mentioned

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The MOSFET in the following circuit is in which configuration? Common Source (CS) Common Drain (CD) Common Gate (CG) None of the mentioned

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1) For the circuit above, identify each transistor, M1 and M2, as corresponding to one of the following possibilities: Common Source (or Common Source with Source Degeneration) Common Gate Source Follower 2) Based on part (1) above, replace M1 and M2 with their simplified two-port models from Problem 1. 3) Reduce the model from part (2) above to a single two port model from Vin to Vout. Be sure to box your expressions for Rin, Rout, and Gm or Av. 4) Based on part (3) above, provide an expression for the DC gain of the above circuit.
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2) Based on part (1) above, replace M1, and M2 with their simplified small-signal two port models from Assignment 1. Note that if you have current source/mirrors, replace them with a corresponding one-port model as discussed in Lecture 6. 1) For the circuit above, identify each transistor, M1 and M2, as corresponding to one of the following possibilities: Common Source (or Common Source with Source Degeneration) Common Gate Source Follower Current Source/Mirror (Example: M: Current Source/Mirror, M2: Common Gate) 3) Reduce the model from part (2) above to a single two port model from Vin to Vout. Be sure to box your expressions for Rin, Rout, and Gm or Av. 4) Based on part (3) above, provide an expression for the DC gain of the above circuit.
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Figure 1 shows a single stage common source MOSFET amplifier circuit. We wish to design the circuit to meet the following design specifications: Load Resistance: RL = 100 KΩ Input Resistance: Ri > 200 KΩ Mid-band Gain: Gv = Vo/Vi = −50 ± 20% Supply Voltage: +15 Volts Circuit Capacitors: CG = 10μF; CS = 47μF; CD = 10μF Figure 1. Common Source MOSFET Amplifier Pre-lab: (a) Design the amplifier to meet the specifications above by choosing values for resistors R1, R2, RD and RS. Begin your design by choosing an appropriate value for the bias current ID. If ID ≈ 0.3 mA, assume VT ≈ 1.7 V, Kn ≈ 0.02 A/V2 and VA = 100 V(λ = 0.01 V−1). Find the small signal approximation of the input resistance Rin where Rin = R1∥R2 Find the small signal approximation of the output resistance Ro, where Ro is given as Ro = RD∥RL∥ro. The small signal mid-band gain of the amplifier is given by Gv = −gmRo where gm = 2knID = kn(VGS−VT) Once you choose ID the DC biasing of the transistor can be found using simple rules of thumb. The voltage VG should be approximately equal to VDD/3 > VT. For maximum symmetry, VD should be biased at the midpoint between VD(Max) and VD(Min). Clearly, the maximum VD is VDD and the minimum VD > VG−Vt. For example, if Vt = 1.7 V and VG = 1/3VDD = 5 V, then VD ≈ 9 V for maximum symmetry.

Figure 1 shows a single stage common source MOSFET amplifier circuit. We wish to design the circuit to meet the following design specifications: Load Resistance: RL = 100 KΩ Input Resistance: Ri > 200 KΩ Mid-band Gain: Gv = Vo/Vi = −50 ± 20% Supply Voltage: +15 Volts Circuit Capacitors: CG = 10μF; CS = 47μF; CD = 10μF Figure 1. Common Source MOSFET Amplifier Pre-lab: (a) Design the amplifier to meet the specifications above by choosing values for resistors R1, R2, RD and RS. Begin your design by choosing an appropriate value for the bias current ID. If ID ≈ 0.3 mA, assume VT ≈ 1.7 V, Kn ≈ 0.02 A/V2 and VA = 100 V(λ = 0.01 V−1). Find the small signal approximation of the input resistance Rin where Rin = R1∥R2 Find the small signal approximation of the output resistance Ro, where Ro is given as Ro = RD∥RL∥ro. The small signal mid-band gain of the amplifier is given by Gv = −gmRo where gm = 2knID = kn(VGS−VT) Once you choose ID the DC biasing of the transistor can be found using simple rules of thumb. The voltage VG should be approximately equal to VDD/3 > VT. For maximum symmetry, VD should be biased at the midpoint between VD(Max) and VD(Min). Clearly, the maximum VD is VDD and the minimum VD > VG−Vt. For example, if Vt = 1.7 V and VG = 1/3VDD = 5 V, then VD ≈ 9 V for maximum symmetry.
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