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The shown configuration has E-NMOS with Vt = 1 V and D-NMOS load with Vt = -1 V connected to VDD = 5 V, if the input voltage (Vi) is 0.5 V the output voltage (v0) is: (a) 0 V (b) 5 V (c) 4 V (d) 1 V

The shown configuration has E-NMOS with Vt = 1 V and D-NMOS load with Vt = -1 V connected to VDD = 5 V, if the input voltage (Vi) is 0.5 V the output voltage (v0) is: (a) 0 V (b) 5 V (c) 4 V (d) 1 V

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The shown configuration has E-NMOS with Vt = 1 V and D-NMOS load with Vt = -1 V connected to VDD = 5 V, if the input voltage (Vi) is 0.5 V the output voltage (v0) is: (a) 0 V (b) 5 V (c) 4 V (d) 1 V

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