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The shown S-R Flip Flop uses matched inverters and is fabricated in a 0.18 μm technology with μnCox = 400 μA/V2, (W/L)n = 0.45/0.18, and PMOST with μpCox = 160 μA/V2, (W/L)p = 1.125/0.18, VDD = 1.8 V, Vtn = |Vtp| = 0.4 V. The drain node capacitance CQ is equal to 100 fF and CR,S = 5 pF. The circuit is at RESET state. One of the shown sub-circuit needs to be used to change the state to SET. Select such a circuit and: Justify rejection of others Determine the clock time needed for the SET state to be ensured Determine the maximum clock frequency

The shown S-R Flip Flop uses matched inverters and is fabricated in a 0.18 μm technology with μnCox = 400 μA/V2, (W/L)n = 0.45/0.18, and PMOST with μpCox = 160 μA/V2, (W/L)p = 1.125/0.18, VDD = 1.8 V, Vtn = |Vtp| = 0.4 V. The drain node capacitance CQ is equal to 100 fF and CR,S = 5 pF. The circuit is at RESET state. One of the shown sub-circuit needs to be used to change the state to SET. Select such a circuit and: Justify rejection of others Determine the clock time needed for the SET state to be ensured Determine the maximum clock frequency

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The shown S-R Flip Flop uses matched inverters and is fabricated in a 0.18 μ m technology with μ n C o x = 400 μ A / V 2 , ( W / L ) n = 0.45 / 0.18 , and PMOST with μ p C o x = 160 μ A / V 2 , ( W / L ) p = 1.125 / 0.18 , V D D = 1.8 V , V t n = | V t p | = 0.4 V . The drain node capacitance C Q is equal to 100 f F and C R , S = 5 p F . The circuit is at RESET state. One of the shown sub-circuit needs to be used to change the state to SET. Select such a circuit and:
  1. Justify rejection of others
  2. Determine the clock time needed for the SET state to be ensured
  3. Determine the maximum clock frequency 1 3

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