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The transistor parameters for the circuit in Figure P16.21 are: VTN = 0.8 V for all enhancement-mode devices, VTN = −2 V for the depletion-mode devices, and kn' = 60 μA/V2 for all devices. The width-to-length ratios of ML2 and ML3 are 1, and those for MD2, MD3, and MD4 are 8. (a) For vX = 5 V, output vO1 is 0.15 V, and the power dissipation in this inverter is to be no more than 250 μW. Determine (W/L)M L1 and (W/L)M D1. (b) For vX = vY = 0, determine vO2.

The transistor parameters for the circuit in Figure P16.21 are: VTN = 0.8 V for all enhancement-mode devices, VTN = −2 V for the depletion-mode devices, and kn' = 60 μA/V2 for all devices. The width-to-length ratios of ML2 and ML3 are 1, and those for MD2, MD3, and MD4 are 8. (a) For vX = 5 V, output vO1 is 0.15 V, and the power dissipation in this inverter is to be no more than 250 μW. Determine (W/L)M L1 and (W/L)M D1. (b) For vX = vY = 0, determine vO2.The transistor parameters for the circuit in Figure P16.21 are: VTN = 0.8 V for all enhancement-mode devices, VTN = −2 V for the depletion-mode devices, and kn' = 60 μA/V2 for all devices. The width-to-length ratios of ML2 and ML3 are 1, and those for MD2, MD3, and MD4 are 8. (a) For vX = 5 V, output vO1 is 0.15 V, and the power dissipation in this inverter is to be no more than 250 μW. Determine (W/L)M L1 and (W/L)M D1. (b) For vX = vY = 0, determine vO2.

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The transistor parameters for the circuit in Figure P16.21 are: V T N = 0.8 V for all enhancement-mode devices, V T N = − 2 V for the depletion-mode
Figure P16.21
devices, and k n ′ = 60 μ A / V 2 for all devices. The width-to-length ratios of M L 2 and M L 3 are 1 , and those for M D 2 , M D 3 , and M D 4 are 8 . (a) For v X = 5 V , output v O 1 is 0.15 V , and the power dissipation in this inverter is to be no more than 250 μ W . Determine ( W / L ) M L 1 and ( W / L ) M D 1 . (b) For v X = v Y = 0 , determine v O 2 .

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