There is a dynamic random access memory (DRAM). (1) What is the minimum capacitance of Cs to have higher than 3 V of Vf after READ operation? Assume Vs = 3.3 V, C Cbit is 1 fF. (2) DRAM requires refresh process because leakage makes the voltage at Cs decrease. What is the minimum refresh period to sustain the voltage Vs higher than 3.0 V ? Assume the leakage current is 1 nA, and Css is 20 fF. Ignore voltage decrease by charge sharing.