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Using the half-circuit analysis, find the differential voltage gain for the circuit (All differential pairs are symmetrical, λ > 0 )

Using the half-circuit analysis, find the differential voltage gain for the circuit (All differential pairs are symmetrical, λ > 0 )

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Using the half-circuit analysis, find the differential voltage gain for the circuit (All differential pairs are symmetrical, λ > 0 )

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Assuming all of the transistors in the circuits are saturated and λ ≠ 0. (a) Draw the half circuit of differential amplifier (4 pts) and (b) find output impedance (4 pts). (c) Calculate the small-signal differential voltage gain (4 pts). (d) Calculate the small-signal common-mode voltage gain for differential output (4 pts). (e) Calculate the common-mode rejection ratio by using the results from (c) and (d) (4 pts).

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For the amplifier below, following design information is provided: VDD = 3.3 V, R = 2.4 kΩ, ISS = 1.8 mA, k1 = k2 = 5 mA/V2, VTH,1 = VTH,2 = 0.5 V, λ = 0.1 V−1, γ = 0, ki′ = μ0Cox, ki = μ0 Cox(W L)i. Assume that both transistors are identical and in the saturation region. Finally, NMOS and PMOS bulk terminals are connected to the ground and VDD, respectively. a) What is the DC bias voltage for M1 and M2 given that the voltage drop across ISS is 0.4 V ? You can neglect the channel length modulation, here. Check that the transistors are in the correct operation-mode. b) The resistors will be realized using identical PMOS transistors M3 and M4. If the transistors to be used will have k3 = k4 = 1.5 mA/V2, what will be their overdrive voltages? Check that the transistors are in the correct operation-mode. c) What is the differential voltage gain AV,diff = Vout/Vid in dB ? d) ISS will be realized as a cascode current source. Assume that the voltage drop of 0.4 V is equally shared by the two transistors, M5 and M6 having k5′ = k6′ = 0.5 mA/V2 and VTH, 5 = VTH, 6 = 0.5 V. Assuming the gate voltages of both transistors are 1 V, find the W/L ratios of each device. Once again, you can neglect the channel length modulation here. e) Considering (d), how would the W/L ratios qualitatively change (increase/decrease/stays the same), if γ > 0 ? Explain your reasoning analytically, i. e. , using appropriate equations. f) Using the cascode current source, calculate the common-mode gain of the circuit AV, CM = Vout /Vin in dB, where Vin . s applied to the gates of both M1 and M2. Assume λ = 0.1 V−1 for M5 and M6. g) Calculate the CMRR of the circuit in dB.
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Assume M1, M2 are ideal (λ = 0) and M3, M4 are not ideal (λ > 0) in the following circuit. All the transistors are operating in saturation region. What is the voltage gain ACM-DM, ADM and the CMRR? Assume ΔRD ≈ 0 for ADM. Make reasonable assumptions when necessary.
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