Question

Notify Me Bookmark

v1(t) and v2(t) represent two sensors with internal resistance of 1 kΩ each, as shown in the circuit bellow. Also, consider both Op-Amps are ideal. Find the expression of the output voltage vO2(t) in terms of v1(t) and v2(t).

v1(t) and v2(t) represent two sensors with internal resistance of 1 kΩ each, as shown in the circuit bellow. Also, consider both Op-Amps are ideal. Find the expression of the output voltage vO2(t) in terms of v1(t) and v2(t).

Image text
  1. v 1 ( t ) and v 2 ( t ) represent two sensors with internal resistance of 1 k Ω each, as shown in the circuit bellow. Also, consider both Op-Amps are ideal. Find the expression of the output voltage v 02 ( t ) in terms of v 1 ( t ) and v 2 ( t ) .

Detailed Answer

0 0

Please enter your email here. You will get email when this question is answered by our tutor.

Doubtrix Logo

Problem is not yet solved!

Click on Notify me to get email when question is answered.

Join Doubtrix with 7-days free trial

  • Icon Correct & Verified Answers
  • Icon No AI-Generated Answers
  • Icon Video Solution for Difficult Questions
  • Icon Work With Experts to Reach at Correct Answers
Notify me Login Sign Up

Similar/Related Questions

Current Mirrors (35 points) This problem introduces current mirrors, which will be covered in more details in future lectures. Consider the circuit shown below (Figure 2). (W/L)1 = 1, (W/L)2 = 5, Rref = 50 kΩ, ignore channel length modulation unless otherwise stated. Assume L1 = L2 = 1 μm. Figure 2 a) (5 points) Assume RL = 10 kΩ. Calculate IL, the current flowing through RL. What is the current mirroring ratio ( IL over Iref , where Iref is the current through Rref )? We want the current mirror to provide a load-independent current as much as possible, so check that M2 is in saturation. b) (5 points) Determine the maximum RL and minimum VOut such that the current mirror still functions with the same current mirroring ratio you calculated in part a). Hint: for the current mirror to function as desired, transistor saturation should be maintained. c) (5 points) Channel length modulation introduces load-dependent errors in the mirroring ratio. Using λ = 0.1 V−1 for L = 1 μm, estimate the percentage error in the mirroring ratio. Here, set RL to its maximum value you got in part b ), and assume that we want the same IL as in parts a) and b). Hint: what should be the new VX and Iref ? d) (4 points) Compute the output resistance, Rout, , looking into the drain of M2. Use λ = 0.1 V−1 and assume the same IL as in parts a) through c). e) (5 points) Now consider redesigning the previous current mirror with source-degenerated transistors as shown in Figure 3. Ignore channel length modulation and body effect ( Assume bulk is tied to source). Transistor sizes remain the same, (WL)1 = 1 and (WL)2 = 5. This circuit has been designed to have the same Iref as in part a). What should the value of Rs2 be if we want the same current mirroring ratio as in a)? f) (5 points) Similarly to part b, determine the maximum RL and minimum VOut such that the current mirror still functions with the same current mirroring ratio as in part e). g) (4 points) Now compute the output resistance, Rout , looking into the drain of M2 (using λ = 0.1 V−1 ). Assume IL as used in parts e) and f ). h) (2 points) Comparing the minimum output voltage and the output resistance of these two current mirrors, comment on the advantages and disadvantages of using source degeneration in a current mirror. Figure 3 Current Mirrors (35 points) This problem introduces current mirrors, which will be covered in more details in future lectures. Consider the circuit shown below (Figure 2). (W/L)1 = 1, (W/L)2 = 5, Rref = 50 kΩ, ignore channel length modulation unless otherwise stated. Assume L1 = L2 = 1 μm. Figure 2 a) (5 points) Assume RL = 10 kΩ. Calculate IL, the current flowing through RL. What is the current mirroring ratio ( IL over Iref , where Iref is the current through Rref )? We want the current mirror to provide a load-independent current as much as possible, so check that M2 is in saturation. b) (5 points) Determine the maximum RL and minimum VOut such that the current mirror still functions with the same current mirroring ratio you calculated in part a). Hint: for the current mirror to function as desired, transistor saturation should be maintained. c) (5 points) Channel length modulation introduces load-dependent errors in the mirroring ratio. Using λ = 0.1 V−1 for L = 1 μm, estimate the percentage error in the mirroring ratio. Here, set RL to its maximum value you got in part b ), and assume that we want the same IL as in parts a) and b). Hint: what should be the new VX and Iref ? d) (4 points) Compute the output resistance, Rout, , looking into the drain of M2. Use λ = 0.1 V−1 and assume the same IL as in parts a) through c). e) (5 points) Now consider redesigning the previous current mirror with source-degenerated transistors as shown in Figure 3. Ignore channel length modulation and body effect ( Assume bulk is tied to source). Transistor sizes remain the same, (WL)1 = 1 and (WL)2 = 5. This circuit has been designed to have the same Iref as in part a). What should the value of Rs2 be if we want the same current mirroring ratio as in a)? f) (5 points) Similarly to part b, determine the maximum RL and minimum VOut such that the current mirror still functions with the same current mirroring ratio as in part e). g) (4 points) Now compute the output resistance, Rout , looking into the drain of M2 (using λ = 0.1 V−1 ). Assume IL as used in parts e) and f ). h) (2 points) Comparing the minimum output voltage and the output resistance of these two current mirrors, comment on the advantages and disadvantages of using source degeneration in a current mirror. Figure 3

Solution
0 0

An NMOS amplifier is shown in Figure 1. Transistor M1 is biased in the saturation region for an amplifier application. The circuit is biased with a resistive voltage divider consisting of R1 and R2, a source degeneration resistor RS, and a load resistor RD. The drain bias current for the design is ID = 500 μA and VDS is 1.625 V. The device parameters are: L = 0.5 μm, W = 10 μm, kn’ = 200 μA/V2, Vtn = 0.5 V, and λn = 0. analyze the frequency response of the amplifier. a) Draw a midband small signal ac equivalent circuit model for the amplifier. For midband you can assume the reactance of Cin is sufficiently low that it is a short circuit. b) Derive an expression for the midband voltage gain transfer function Vout /Vsig. The amplified output signal is taken from the drain terminal and Vout = Vd. Write your gain function in terms of variables only. c) Evaluate the midband gain and calculate a value both in V/V and dB. d) Analyze the frequency response of the input network including the capacitor Cin. Find an expression for the transfer function H1(jω) = Vg/Vsig. e) Evaluate H1(jω) = Vg/Vsig and make a Bode plot of the magnitude of H1(jω). The x-axis is ω (log scale) and the y-axis is the magnitude in dB. f) Use the LTSPICE circuit template and verify the frequency response of the amplifier circuit. Include a copy of the schematic and the frequency response plot. Use 20 points per decade and a frequency span of 0.1 Hz to 100 Hz.
Solution
0 0

Consider the open-loop circuit (on the left) and closed-loop circuit (on the right) shown in Figure 1 below. In this problem, the open-loop circuit (on the left) will be used to analyze the open-loop behavior of the closed-loop circuit (on the right). closed - loof ciruit Figure 1. Open-loop (left) and closed-loop (right) circuits for Problem 1. Here are the problem parameters:The NMOS devices have gmn = 6 mA/V and rdsn = 25 kΩ. The PMOS devices have gmp = 3 mA/V and rdsp = 15 kΩ. Resistor values are R1 = 1 kΩ and R2 = 3 kΩ. a) Referring to the open-loop circuit of Figure 1, determine the numerical open-loop gain Av. OL = Vout /Vin . For the purposes of this analysis, as we have done a million times before (reminder: this is the 2 nd semester of electronics, so this should not be your first electronics rodeo), you should deactivate all sources in the circuit, except Vin. . b) Referring to the open-loop circuit of Figure 1, determine the numerical open-loop output resistance Rout, oL. , i. e. , the resistance seen looking in at the output node Vout. . You should deactivate all sources in the circuit; feel free to add an appropriate test source(s), if you think you need to do that. c) Referring to the open-loop circuit of Figure 1, determine the numerical loop gain from the test source to the output node: LG = |Vout /Vtest | For the purposes of this analysis, you should deactivate all sources in the circuit, except Vtest. . Also, note that the way the loop gain is defined, it will be a positive-valued quantity. Explain why we want to use a positive loop gain for determining the closed-loop performance [see, e. g. , parts (d) and (e) below]. Your answer for this part should be both i) specific to this problem and ii) generalized to any closed-loop circuit with negative feedback. You are strongly encouraged to consider incorporating a generalized block diagram to help strengthen your argument(s). d) Referring to the closed-loop circuit of Figure 1, determine the numerical closed-loop gain Av, CL = Vout /Vin . Rather than solving the closed-loop circuit of Figure 1 directly for the closed-loop gain, you should instead utilize the results of the previous parts to determine Av, cL. Here, I need to remind you that you should do as you have been (hopefully) doing on the previous parts: first, state the equation you will use to determine Av, cL in terms of, e. g. , Av. ol. and/or Rout, ol and/or LG (i. e. , resist the temptation to dive straight into the numerical values, but feel free to write your equation in terms of Av, ol and/or Rout, ol. and/or LG instead of gmn, gmp, rdsn, rdpp , R1, R2 ), and then plug the numbers in to your equation, and then box your numerical answer along with all the things that we have expected of your numerical quantities since day one. Make it really easy for me to find the equation you used (same story for all of the parts of this problem). e) Referring to the closed-loop circuit of Figure 1, determine the numerical closed-loop output resistance Rout, CL. Rather than solving the closed-loop circuit of Figure 1 directly for the closed-loop output resistance, you should instead follow the same guidance that was given for part (d) of this problem.

Solution
0 0