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W/L ratio that results in Veff = 200mV at ID = 0.5 mA, ignoring channel-length modulation (CLM) b. If this device is used in a common-source amplifier (Fig 1(a)), what is the maximum achievable gain, independent of drain resistance? c. Find the gain for the circuit when using the maximum value of drain resistor which still results in the circuit remaining in saturation. d. If M1 is replaced with a PMOS cascode (biased at 0.5 mA and both devices sized according to 1(a)), with the lower (cascode) device biased at 2 V gate voltage, what is the maximum achievable gain, independent of drain resistance? e. Find the gain for the circuit when using the maximum value of drain resistor which still results in all transistors remaining in saturation. f. Discuss what fundamentally limits the gain of these circuits. Fig 1 For the questions below, assume the following device parameters: Kn

W/L ratio that results in Veff = 200mV at ID = 0.5 mA, ignoring channel-length modulation (CLM) b. If this device is used in a common-source amplifier (Fig 1(a)), what is the maximum achievable gain, independent of drain resistance? c. Find the gain for the circuit when using the maximum value of drain resistor which still results in the circuit remaining in saturation. d. If M1 is replaced with a PMOS cascode (biased at 0.5 mA and both devices sized according to 1(a)), with the lower (cascode) device biased at 2 V gate voltage, what is the maximum achievable gain, independent of drain resistance? e. Find the gain for the circuit when using the maximum value of drain resistor which still results in all transistors remaining in saturation. f. Discuss what fundamentally limits the gain of these circuits. Fig 1 For the questions below, assume the following device parameters: Kn

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W/L ratio that results in Veff = 200mV at ID = 0.5 mA, ignoring channel-length modulation (CLM) b. If this device is used in a common-source amplifier (Fig 1(a)), what is the maximum achievable gain, independent of drain resistance? c. Find the gain for the circuit when using the maximum value of drain resistor which still results in the circuit remaining in saturation. d. If M1 is replaced with a PMOS cascode (biased at 0.5 mA and both devices sized according to 1(a)), with the lower (cascode) device biased at 2 V gate voltage, what is the maximum achievable gain, independent of drain resistance? e. Find the gain for the circuit when using the maximum value of drain resistor which still results in all transistors remaining in saturation. f. Discuss what fundamentally limits the gain of these circuits. Fig 1 For the questions below, assume the following device parameters: Kn

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10a) (15 Points) In the following circuit, an NMOS transistor is used to switch the current to the LED. Assume the following parameters: Microcontroller: vO = 4.6 V iOH < −5 mA and vOL = 0.4 V, iOL < 8 mA LED: vf = 2.0 V, PLED−max = 200 mW Desired LED current 100 mA Transistor: vT = 1.0 V, RDS(ON) = 0.5 Ω, iD−max = 500 mA a. When the output of the microcontroller is low, what is the operating region of the transistor? b. When the output of the microcontroller is high, what is the operating region of the transistor? c. With the microcontroller output high, and the transistor in the ohmic region, what value of R results in an on-state LED current of 100 mA? d. What standard value of resistor (Table is on page 33 of the text) comes closest to the desired LED current? 10b) Suppose we rearrange the NMOS circuit in problem 10 as shown. Using the same parameters as in the previous problem, answer the following: a. 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Current Mirrors (35 points) This problem introduces current mirrors, which will be covered in more details in future lectures. Consider the circuit shown below (Figure 2). (W/L)1 = 1, (W/L)2 = 5, Rref = 50 kΩ, ignore channel length modulation unless otherwise stated. Assume L1 = L2 = 1 μm. Figure 2 a) (5 points) Assume RL = 10 kΩ. Calculate IL, the current flowing through RL. What is the current mirroring ratio ( IL over Iref , where Iref is the current through Rref )? We want the current mirror to provide a load-independent current as much as possible, so check that M2 is in saturation. b) (5 points) Determine the maximum RL and minimum VOut such that the current mirror still functions with the same current mirroring ratio you calculated in part a). Hint: for the current mirror to function as desired, transistor saturation should be maintained. c) (5 points) Channel length modulation introduces load-dependent errors in the mirroring ratio. Using λ = 0.1 V−1 for L = 1 μm, estimate the percentage error in the mirroring ratio. Here, set RL to its maximum value you got in part b ), and assume that we want the same IL as in parts a) and b). Hint: what should be the new VX and Iref ? d) (4 points) Compute the output resistance, Rout, , looking into the drain of M2. Use λ = 0.1 V−1 and assume the same IL as in parts a) through c). e) (5 points) Now consider redesigning the previous current mirror with source-degenerated transistors as shown in Figure 3. Ignore channel length modulation and body effect ( Assume bulk is tied to source). Transistor sizes remain the same, (WL)1 = 1 and (WL)2 = 5. This circuit has been designed to have the same Iref as in part a). What should the value of Rs2 be if we want the same current mirroring ratio as in a)? f) (5 points) Similarly to part b, determine the maximum RL and minimum VOut such that the current mirror still functions with the same current mirroring ratio as in part e). g) (4 points) Now compute the output resistance, Rout , looking into the drain of M2 (using λ = 0.1 V−1 ). Assume IL as used in parts e) and f ). h) (2 points) Comparing the minimum output voltage and the output resistance of these two current mirrors, comment on the advantages and disadvantages of using source degeneration in a current mirror. Figure 3 Current Mirrors (35 points) This problem introduces current mirrors, which will be covered in more details in future lectures. Consider the circuit shown below (Figure 2). (W/L)1 = 1, (W/L)2 = 5, Rref = 50 kΩ, ignore channel length modulation unless otherwise stated. Assume L1 = L2 = 1 μm. Figure 2 a) (5 points) Assume RL = 10 kΩ. Calculate IL, the current flowing through RL. What is the current mirroring ratio ( IL over Iref , where Iref is the current through Rref )? We want the current mirror to provide a load-independent current as much as possible, so check that M2 is in saturation. b) (5 points) Determine the maximum RL and minimum VOut such that the current mirror still functions with the same current mirroring ratio you calculated in part a). Hint: for the current mirror to function as desired, transistor saturation should be maintained. c) (5 points) Channel length modulation introduces load-dependent errors in the mirroring ratio. Using λ = 0.1 V−1 for L = 1 μm, estimate the percentage error in the mirroring ratio. Here, set RL to its maximum value you got in part b ), and assume that we want the same IL as in parts a) and b). Hint: what should be the new VX and Iref ? d) (4 points) Compute the output resistance, Rout, , looking into the drain of M2. Use λ = 0.1 V−1 and assume the same IL as in parts a) through c). e) (5 points) Now consider redesigning the previous current mirror with source-degenerated transistors as shown in Figure 3. Ignore channel length modulation and body effect ( Assume bulk is tied to source). Transistor sizes remain the same, (WL)1 = 1 and (WL)2 = 5. This circuit has been designed to have the same Iref as in part a). What should the value of Rs2 be if we want the same current mirroring ratio as in a)? f) (5 points) Similarly to part b, determine the maximum RL and minimum VOut such that the current mirror still functions with the same current mirroring ratio as in part e). g) (4 points) Now compute the output resistance, Rout , looking into the drain of M2 (using λ = 0.1 V−1 ). Assume IL as used in parts e) and f ). h) (2 points) Comparing the minimum output voltage and the output resistance of these two current mirrors, comment on the advantages and disadvantages of using source degeneration in a current mirror. Figure 3

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