We wish to design the MOS cascode of Fig. 11.95 for an input pole of 5 GHz and an output pole of 10 GHz. Assume M1 and M2 are identical, ID = 0.5 mA, CGS = (2/3)WLCox, Cox = 12 fF/µm2, µnCox = 100 µA/V2, λ = 0, L = 0.18 µm, and CGD = C0W, where C0 = 0.2 fF/µm denotes the gate-drain capacitance per unit width. Determine the maximum allowable values of RG, RD, and the voltage gain. Use Miller’s approximation for CGD1. Assume an overdrive voltage of 200 mV for each transistor.
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We wish to design the MOS cascode of Fig. 11.95 for an input pole of 5 GHz and an output pole of 10 GHz. Assume M1 and M2 are identical, ID = 0.5 mA, CGS = (2/3)WLCox, Cox = 12 fF/µm2, µnCox = 100 µA/V2, λ = 0, L = 0.18 µm, and CGD = C0W, where C0 = 0.2 fF/µm denotes the gate-drain capacitance per unit width. Determine the maximum allowable values of RG, RD, and the voltage gain. Use Miller’s approximation for CGD1. Assume an overdrive voltage of 200 mV for each transistor.
