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What are the conditions to keep our transistor in saturation, linear, and cut-off regions? Why is los very low at lower VGS even if VDS is pretty high? Write down the step by step methods to extract gds from the measured value. Why is the following circuit called diode-connected? Why do we need to provide negative voltage (VG, VD) instead of positive (for pmos)?

What are the conditions to keep our transistor in saturation, linear, and cut-off regions? Why is los very low at lower VGS even if VDS is pretty high? Write down the step by step methods to extract gds from the measured value. Why is the following circuit called diode-connected? Why do we need to provide negative voltage (VG, VD) instead of positive (for pmos)?

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  1. What are the conditions to keep our transistor in saturation, linear, and cut-off regions?
  2. Why is los very low at lower V G S even if V 0 S is pretty high?
  3. Write down the step by step methods to extract gos from the measured value.
  4. Why is the following circuit called diode-connected?
  5. Why do we need to provide negative voltage ( V G , V D ) instead of positive (for pmos)?

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We observe that NFETs do not transmit a ‘1’ very well and PFETs do not transmit a ‘0’ very well because with VGS = VDD and VDS = VDD in an NFET, the Source terminal will charge up only until it reaches VDD-VTn because at higher voltages, the Gate-Source voltage difference is less than the Threshold Voltage VTn of the NFET causing it to ‘turn-off’ when the Source Terminal rises to within a VTn of VDD. Sketch the output voltage characteristic if the PFET and the NFET positions were swapped as shown below? i) Write down the voltages at A, B, C, D, E, F, G in the following circuit, assuming that the initial voltage on each node is 2.5 volts. The relevant transistor parameters are, VDD = 5 V, VTn = 1 V and ∣VTp∣ = 0.7 V

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Transient Point (Threshold Voltage) In practice, in an inverter circuit, there is an unstable transient point at which both transistors are on and in saturation mode. The input voltage (connected to the gate) for this point is called the threshold voltage (Vin = VTH). At this point, VGS/VSG of the NMOS / PMOS is equal to Vin/VDD-Vin. Note that this threshold voltage is different from the intrinsic threshold voltage of transistors (VTN or VTP). Derive an expression for this threshold voltage [RP2]. Verify your work with the expression below: What happens to VTH when Kp > Kn, Kp = Kn, and Kp < Kn? What haapens when Kp approaches 0 or when Kn approaches 0? Use words to generalize how various Kn and Kp values change VTH and describe how the values of Kn and Kp can be tuned by parallel MOSFET connection [RP2]. Noise Margin Please read section 6.9.4 of the textbook or search on the internet about noise margin. Sketch a typical transfer function of an inverter (non-ideal one) with 1 PMOS and 1 NMOS and label VIL, VOH, VOL,VIH, NMH, and NML on your sketch [RP3]. Why is the metric of noise margin useful [RP3]? Make a reasoned guess about how the change in the threshold voltage VTH (or the change in Kn/Kp ) affects each of the noise margin parameters [RP4].

Transient Point (Threshold Voltage) In practice, in an inverter circuit, there is an unstable transient point at which both transistors are on and in saturation mode. The input voltage (connected to the gate) for this point is called the threshold voltage (Vin = VTH). At this point, VGS/VSG of the NMOS / PMOS is equal to Vin/VDD-Vin. Note that this threshold voltage is different from the intrinsic threshold voltage of transistors (VTN or VTP). Derive an expression for this threshold voltage [RP2]. Verify your work with the expression below: What happens to VTH when Kp > Kn, Kp = Kn, and Kp < Kn? What haapens when Kp approaches 0 or when Kn approaches 0? Use words to generalize how various Kn and Kp values change VTH and describe how the values of Kn and Kp can be tuned by parallel MOSFET connection [RP2]. Noise Margin Please read section 6.9.4 of the textbook or search on the internet about noise margin. Sketch a typical transfer function of an inverter (non-ideal one) with 1 PMOS and 1 NMOS and label VIL, VOH, VOL,VIH, NMH, and NML on your sketch [RP3]. Why is the metric of noise margin useful [RP3]? Make a reasoned guess about how the change in the threshold voltage VTH (or the change in Kn/Kp ) affects each of the noise margin parameters [RP4].
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