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What are the voltage levels at nodes W, X, Y and Z in the circuit below in the steady state, assuming that input A goes from VD to 0 whereas inputs B through E go from 0 to VDD? The threshold voltage of NMOS transistors is VT. Hint: You may ignore the body bias effect.

What are the voltage levels at nodes W, X, Y and Z in the circuit below in the steady state, assuming that input A goes from VD to 0 whereas inputs B through E go from 0 to VDD? The threshold voltage of NMOS transistors is VT. Hint: You may ignore the body bias effect.

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What are the voltage levels at nodes W , X , Y and Z in the circuit below in the steady state, assuming that input A goes from V D to 0 whereas inputs B through E go from 0 to V D D ? The threshold voltage of NMOS transistors is V T . Hint: You may ignore the body bias effect.

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