What is the propagation delay for a falling edge in picoseconds for a 2 -input NOR gate in a 0.35μm CMOS process if the total capacitance on the output of this logic gate is 65.9fF ? Do NOT use the Elmore formula. Use: W/Lp = 12.2, W/Ln = 7.2, VDD = 3.3 V, VTN = 0.7 V, VTP = -0.7 V, k'n = 100 μA/V^2, k'p = 40 μA/V^2
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What is the propagation delay for a falling edge in picoseconds for a 2 -input NOR gate in a 0.35μm CMOS process if the total capacitance on the output of this logic gate is 65.9fF ? Do NOT use the Elmore formula. Use: W/Lp = 12.2, W/Ln = 7.2, VDD = 3.3 V, VTN = 0.7 V, VTP = -0.7 V, k'n = 100 μA/V^2, k'p = 40 μA/V^2
