You are required to design a SRAM cell with the minimum area in 65 nm

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You are required to design a SRAM cell with the minimum area in 65 nm CMOS process. Process parameters are given next to the figure below. VDD = 1 VVtn = Vtp = 0.3 VCox = 17 fF/μm2 μn = 3 μp = 0.06 m2 /VsLmin = 65 nmWmin = 130 nmλ = 30 nm a) [2] Calculate the smallest possible sizes of M3, M5 to satisfy the writability condition. (Hint: please assume that the read speed is not important). W3 = W5 =

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Question 3. [8] You are required to design a SRAM cell with the minimum area in

65 n m

CMOS process. Process parameters are given next to the figure below.

\begin{array}{l} V_{D D} = 1 V \\ V_{t n} = V_{t p} = 0.3 V \\ C_{o x} = 17 f F / μ m^{2} \\ μ_{n} = 3 μ_{p} = 0.06 m^{2} / V s \\ L_{min} = 65 n m \\ W_{min} = 130 n m \\ λ = 30 n m \end{array}

a) [2] Calculate the smallest possible sizes of M3, M5 to satisfy the writability condition. (Hint: please assume that the read speed is not important).